
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Waveform of Interrupt Timing (1)
t WC
Industrial and Commercial Temperature Ranges
ADDR "A"
INTERRUPT SET ADDRESS
(2)
(3)
t AS
t WR
(4)
CE "A"
R/ W "A"
t INS (3)
INT "B"
5624 drw 17
t RC
ADDR "B"
CE "B"
OE "B"
t AS (3)
t INR
(3)
INTERRUPT CLEAR ADDRESS
(2)
I NT "B"
5624 drw 18
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Flag Truth Table III.
3. Timing depends on which enable signal ( CE or R/ W ) is asserted last.
4. Timing depends on which enable signal ( CE or R/ W ) is de-asserted first.
20
6.42